EP4CE40 datasheet(208/488 Pages) ALTERA

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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

f For more information about configuring multiple Altera devices in the same

configuration chain, refer to Configuring Mixed Altera FPGA Chains in volume 2 of the

Configuration Handbook.

FPP Configuration Timing

Figure 8–22 shows the timing waveform for the FPP configuration when using an

external host.

Table 8–13 lists the FPP configuration timing parameters for Cyclone IV devices.

Figure 8–22. FPP Configuration Timing Waveform (1)

Notes to Figure 8–22:

(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE

are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.

(2) After power up, the Cyclone IV device holds nSTATUS low during POR delay.

(3) After power up, before and during configuration, CONF_DONE is low.

(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.

(5) DATA[7..0] is available as a user I/O pin after configuration; the state of the pin depends on the dual-purpose pin

settings.

nCONFIG

nSTATUS (2)

CONF_DONE (3)

DCLK

DATA[7..0]

User I/O

INIT_DONE

Byte 0

Byte 1

Byte 2

Byte 3

Byte n-1

tCD2UM

tCF2ST1

tCF2CD

tCFG

tCH tCL

tDH

tDSU

tCF2CK

tSTATUS

tCLK

tCF2ST0

tST2CK

User Mode

(5)

Tri-stated with internal pull-up resistor

(4)

User Mode

Byte n

User mode

Table 8–13. FPP Timing Parameters for Cyclone IV Devices (Part 1 of 2)

Symbol

Parameter

Minimum

Maximum

Unit

Cyclone IV (1)

Cyclone IV E (2)

Cyclone IV (1)

Cyclone IV E (2)

tCF2CD

nCONFIG

low to

CONF_DONE

low

—

500

tCF2ST0

nCONFIG

low to

nSTATUS

low

—

500

tCFG

nCONFIG

low pulse

width

500

—

tSTATUS

nSTATUS

low pulse

width

230 (3)

µs

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