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TMS320F2810PBKA Datasheet(PDF) 24 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 173 page  24 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated 5.5 Power Consumption Summary (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins. (3) MAX numbers are at 125°C, and MAX voltage (VDD = 1.89 V; VDDIO, VDD3VFL, VDDA = 3.47 V). (4) IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1. Table 5-1. TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT MODE TEST CONDITIONS IDD IDDIO (1) IDD3VFL IDDA (2) TYP MAX(3) TYP MAX(3) TYP MAX(3) TYP MAX(3) Operational All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is continuously transmitted out of the SCIA, SCIB, and CAN ports. The hardware multiplier is exercised. Code is running out of flash with 5 wait- states. 195 mA(4) 230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA IDLE • Flash is powered down • XCLKOUT is turned off • All peripheral clocks are on, except ADC 125 mA 150 mA 5 mA 10 mA 2 µA 4 µA 1 µA 20 µA STANDBY • Flash is powered down • Peripheral clocks are turned off • Pins without an internal PU/PD are tied high/low 5 mA 10 mA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA HALT • Flash is powered down • Peripheral clocks are turned off • Pins without an internal PU/PD are tied high/low • Input clock is disabled 70 µA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA NOTE HALT and STANDBY modes cannot be used when the PLL is disabled. |
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