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TMS320F2810PBKA Datasheet(PDF) 78 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 173 page  78 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. (3) C = CLKRX low pulse width = P D = CLKRX high pulse width = P Table 5-48. McBSP Switching Characteristics(1)(2) NO. PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5(3) D + 5(3) ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5(3) C + 5(3) ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns CLKR ext 3 27 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int 0 4 ns CLKX ext 3 27 M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX int 8 ns CLKX ext 14 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. CLKX int 9 ns CLKX ext 28 Delay time, CLKX high to DX valid. Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY = 01b or 10b) modes. DXENA = 0 CLKX int 8 CLKX ext 14 DXENA = 1 CLKX int P + 8 CLKX ext P + 14 M8 ten(CKXH-DX) Enable time, CLKX high to DX driven. Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY = 01b or 10b) modes. DXENA = 0 CLKX int 0 ns CLKX ext 6 DXENA = 1 CLKX int P CLKX ext P + 6 M9 td(FXH-DXV) Delay time, FSX high to DX valid. Only applies to first bit transmitted when in Data Delay 0 (XDATDLY = 00b) mode. DXENA = 0 FSX int 8 ns FSX ext 14 DXENA = 1 FSX int P + 8 FSX ext P + 14 M10 ten(FXH-DX) Enable time, FSX high to DX driven. Only applies to first bit transmitted when in Data Delay 0 (XDATDLY = 00b) mode. DXENA = 0 FSX int 0 ns FSX ext 6 DXENA = 1 FSX int P FSX ext P + 6 |
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