TMS320F2810PBKA datasheet(73/173 Pages) TI

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ADC Power Up Delay

ADC Ready for Conversions

PWDNBG

PWDNREF

PWDNADC

Request for

ADC Conversion

d(BGR)

d(PWD)

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Specifications

5.12.5.15.2 ADC Power-Up Control Bit Timing

Figure 5-36. ADC Power-Up Control Bit Timing

(1)

These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If

conversions are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at

the same time.

Table 5-44. ADC Power-Up Delays(1)

MIN

TYP

MAX

UNIT

td(BGR)

Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3

enabled.

td(PWD)

Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register

(ADCPWDN) is to be set to 1 before any ADC conversions are initiated.

µs

5.12.5.15.3 Detailed Description

5.12.5.15.3.1 Reference Voltage

The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP

is set to 2.0 V and ADCVREFM is set to 1.0 V.

5.12.5.15.3.2 Analog Inputs

The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at

a time. These inputs are software-selectable.

5.12.5.15.3.3 Converter

The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with

low power consumption.

5.12.5.15.3.4 Conversion Modes

The conversion can be performed in two different conversion modes:

•

Sequential sampling mode (SMODE = 0)

•

Simultaneous sampling mode (SMODE = 1)

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