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TMS320F2810PBKA Datasheet(PDF) 82 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 173 page  M51 M50 M47 CLKX FSX DX DR M44 M48 M49 M43 LSB MSB M52 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 82 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG Table 5-53. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)(2) NO. MASTER SLAVE UNIT MIN MAX MIN MAX M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns M52 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG Table 5-54. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns Figure 5-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 |
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