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TMS320F2810PBKA Datasheet(PDF) 96 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 96 Page - Texas Instruments |
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96 / 173 page ![]() INT1 to INT12 INT14 C28x CPU TINT2 TINT0 PIE CPU-TIMER 2 (Reserved for DSP/BIOS) INT13 TINT1 XINT13 CPU-TIMER 0 CPU-TIMER 1 96 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Detailed Description Copyright © 2001–2019, Texas Instruments Incorporated In the F281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 6-2. A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 6-2. CPU-Timer Interrupts Signals and Output Signal The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 6-3 are used to configure the timers. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide. |
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