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TMS320F2810PBKA Datasheet(PDF) 80 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 173 page ![]() CLKX FSX DX M30 M31 DR M28 M24 M29 M25 LSB MSB M32 M33 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 (n-2) (n-3) (n-4) Bit(n-1) 80 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated 5.12.5.16.2 McBSP as SPI Master or Slave Timing (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG Table 5-49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)(2) NO. MASTER SLAVE UNIT MIN MAX MIN MAX M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns M33 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG Table 5-50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P ns M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P ns M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns Figure 5-41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 |
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