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TMS320F2810PBKA Datasheet(PDF) 48 Page - Texas Instruments

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Part # TMS320F2810PBKA
Description  TMS320F281x Digital Signal Processors
PDF  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 48 Page - Texas Instruments

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t
d(IDLE-XCOH)
32 SYSCLKOUT Cycles
X1/XCLKIN
XCLKOUT
(H)
Wake-up Latency
Flushing Pipeline
t
d(wake)
A
B
C
D
Device
Status
E
G
F
PLL Lock-up Time
XNMI
Normal
Execution
HALT
HALT
t
w(WAKE-XNMI)
t
p
Oscillator Start-up Time
48
TMS320F2810, TMS320F2811, TMS320F2812
SPRS174U – APRIL 2001 – REVISED JULY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812
Specifications
Copyright © 2001–2019, Texas Instruments Incorporated
Table 5-20. HALT Mode Timing Requirements
MIN
MAX
UNIT
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2tc(CI)
cycles
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8tc(CI)
cycles
Table 5-21. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
32tc(SCO)
45tc(SCO)
cycles
tp
PLL lock-up time
131072tc(CI)
cycles
td(WAKE)
Delay time, PLL lock to program execution resume
•
Wake up from flash
–
Flash module in sleep state
1125tc(SCO)
cycles
•
Wake up from SARAM
35tc(SCO)
cycles
A.
IDLE instruction is executed to put the device into HALT mode.
B.
The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
C.
Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT
mode and consumes absolute minimum power.
D.
When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2tc(CI) is
applicable when an external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be
added to this parameter.
E.
When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G.
Normal operation resumes.
H.
XCLKOUT = SYSCLKOUT
Figure 5-21. HALT Wakeup Using XNMI



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