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TMS320F2810PBKA Datasheet(PDF) 68 Page - Texas Instruments

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Part # TMS320F2810PBKA
Description  TMS320F281x Digital Signal Processors
PDF  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 68 Page - Texas Instruments

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XCLKOUT
(/1 Mode)
XHOLD
XR/
,
,
,
W
XZCS0AND1
XZCS2
XZCS6AND7
XD[15:0]
Valid
XHOLDA
t
d(HL-Hiz)
t
d(HH-HAH)
High-Impedance
XA[18:0]
Valid
Valid
High-Impedance
t
d(HH-BV)
t
d(HL-HAL)
See Note (A)
See Note (B)
68
TMS320F2810, TMS320F2811, TMS320F2812
SPRS174U – APRIL 2001 – REVISED JULY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812
Specifications
Copyright © 2001–2019, Texas Instruments Incorporated
5.12.5.14 XHOLD/XHOLDA Timing
(1)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2)
The state of XHOLD is latched on the rising edge of XTIMCLK.
Table 5-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)(1)(2)
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
A.
All pending XINTF accesses are completed.
B.
Normal XINTF operation resumes.
Figure 5-33. External Interface Hold Waveform



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