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TMS320F2810PBKA Datasheet(PDF) 27 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 173 page ![]() 27 TMS320F2810, TMS320F2811, TMS320F2812 www.ti.com SPRS174U – APRIL 2001 – REVISED JULY 2019 Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated (1) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5. (2) The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST. 5.6 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = IOH MAX 2.4 V IOH = 50 µA VDDIO – 0.2 VOL Low-level output voltage IOL = IOL MAX 0.4 V IIL Input current (low level) With pullup VDDIO = 3.3 V, VIN = 0 V All I/Os(1) (including XRS) except EVB –80 –140 –190 µA GPIOB/EVB –13 –25 –35 With pulldown VDDIO = 3.3 V, VIN = 0 V ±2 IIH Input current (high level) With pullup VDDIO = 3.3 V, VIN = VDD ±2 µA With pulldown(2) VDDIO = 3.3 V, VIN = VDD 28 50 80 IOZ Leakage current (for pins without internal PU/PD), high-impedance state (off-state) VO = VDDIO or 0 V ±2 µA Ci Input capacitance 2 pF Co Output capacitance 3 pF (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements 5.7 Thermal Resistance Characteristics for 179-Ball ZHH Package °C/W(1) RΘJC Junction-to-case thermal resistance 16.08 RΘJA Junction-to-free air thermal resistance 42.57 PsiJT Junction-to-package top 0.658 (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements 5.8 Thermal Resistance Characteristics for 179-Ball GHH Package °C/W(1) RΘJC Junction-to-case thermal resistance 16.08 RΘJA Junction-to-free air thermal resistance 42.57 PsiJT Junction-to-package top 0.658 |
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