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TMS320F2810PBKA Datasheet(PDF) 31 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 173 page ![]() 31 TMS320F2810, TMS320F2811, TMS320F2812 www.ti.com SPRS174U – APRIL 2001 – REVISED JULY 2019 Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated 5.12.2 Power Supply Sequencing TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. • Option 1: In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the recommended approach. • Option 2: Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins. 1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device. See Figure 5-7 for power-on reset timing. • Power-Down Sequencing: During power-down, the device reset should be asserted low (8 µs, minimum) before the VDD supply reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates. NOTE The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V. |
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