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TMS320F2810PBKA Datasheet(PDF) 81 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 173 page ![]() Bit 0 Bit 0 CLKX FSX DX DR M35 M37 M40 M39 M38 M34 LSB MSB M41 M42 Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-3) (n-4) (n-4) 81 TMS320F2810, TMS320F2811, TMS320F2812 www.ti.com SPRS174U – APRIL 2001 – REVISED JULY 2019 Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG Table 5-51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)(2) NO. MASTER SLAVE UNIT MIN MAX MIN MAX M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns M42 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG Table 5-52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low P + 6 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns Figure 5-42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 |
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