TMS320F2810PBKA datasheet(51/173 Pages) TI

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SPISIMO

SPISOMI

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

SPISIMO Data

Must Be Valid

SPISOMI Data Is Valid

SPISTE

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Specifications

(1)

The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2)

tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3)

Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4)

tc(LCO) = LSPCLK cycle time

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

5.12.5.6 Serial Peripheral Interface (SPI) Slave Mode Timing

Table 5-24 lists the slave mode timing (clock phase = 0) and Table 5-25 lists the slave mode timing (clock

phase = 1). Figure 5-24 and Figure 5-25 show the timing waveforms.

Table 5-24. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)

NO.

PARAMETER

MIN

MAX

UNIT

tc(SPC)S

Cycle time, SPICLK

4tc(SYSCLK)

tw(SPC1)S

Pulse duration, SPICLK first pulse

2tc(SYSCLK) – 1

tw(SPC2)S

Pulse duration, SPICLK second pulse

2tc(SYSCLK) – 1

td(SOMI)S

Delay time, SPICLK to SPISOMI valid

tv(SOMI)S

Valid time, SPISOMI data valid after SPICLK

tsu(SIMO)S

Setup time, SPISIMO valid before SPICLK

1.5tc(SYSCLK)

th(SIMO)S

Hold time, SPISIMO data valid after SPICLK

1.5tc(SYSCLK)

tsu(STE)S

Setup time, SPISTE active before SPICLK

1.5tc(SYSCLK)

th(STE)S

Hold time, SPISTE inactive after SPICLK

1.5tc(SYSCLK)

Figure 5-24. SPI Slave Mode External Timing (Clock Phase = 0)

TMS320F2810PBKA Datasheet(PDF) 51 Page - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 51 Page - Texas Instruments

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