TMS320F2810PBKA datasheet(38/173 Pages) TI

38 / 173 page

TMS320F2810, TMS320F2811, TMS320F2812

SPRS174U – APRIL 2001 – REVISED JULY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Specifications

5.12.4.2 Clock Requirements and Characteristics

5.12.4.2.1 Input Clock Requirements

The clock provided at the XCLKIN pin generates the internal CPU clock cycle.

Table 5-5. Input Clock Frequency

PARAMETER

MIN

TYP

MAX

UNIT

Input clock frequency

Resonator

MHz

Crystal

XCLKIN

Without PLL

150

With PLL

100

Limp mode clock frequency

MHz

Table 5-6. XCLKIN Timing Requirements – PLL Bypassed or Enabled

NO.

MIN

MAX

UNIT

tc(CI)

Cycle time, XCLKIN

6.67

250

tf(CI)

Fall time, XCLKIN

C10

tr(CI)

Rise time, XCLKIN

C11

tw(CIL)

Pulse duration, X1/XCLKIN low as a percentage of tc(CI)

C12

tw(CIH)

Pulse duration, X1/XCLKIN high as a percentage of tc(CI)

Table 5-7. XCLKIN Timing Requirements – PLL Disabled

NO.

MIN

MAX

UNIT

tc(CI)

Cycle time, XCLKIN

6.67

250

tf(CI)

Fall time, XCLKIN

Up to 30 MHz

30 MHz to 150 MHz

C10

tr(CI)

Rise time, XCLKIN

Up to 30 MHz

30 MHz to 150 MHz

C11

tw(CIL)

Pulse duration, X1/XCLKIN low as a percentage of tc(CI)

XCLKIN

≤ 120 MHz

120 < XCLKIN

≤ 150 MHz

C12

tw(CIH)

Pulse duration, X1/XCLKIN high as a percentage of tc(CI)

XCLKIN

≤ 120 MHz

120 < XCLKIN

≤ 150 MHz

Table 5-8. Possible PLL Configuration Modes

PLL MODE

REMARKS

SYSCLKOUT

PLL Disabled

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.

Clock input to the CPU (CLKIN) is directly derived from the clock signal present at

the X1/XCLKIN pin.

XCLKIN

PLL Bypassed

Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is

bypassed. However, the /2 module in the PLL block divides the clock input at the

X1/XCLKIN pin by two before feeding it to the CPU.

XCLKIN/2

PLL Enabled

Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the

PLL block now divides the output of the PLL by two before feeding it to the CPU.

(XCLKIN * n) / 2

TMS320F2810PBKA Datasheet(PDF) 38 Page - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL