TMS320F2810PBKA datasheet(33/173 Pages) TI

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TMS320F2810, TMS320F2811, TMS320F2812

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SPRS174U – APRIL 2001 – REVISED JULY 2019

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Specifications

5.12.3 Reset Timing

(1)

If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.

(2)

Dependent on crystal/resonator and board design.

(3)

The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the

TMS320x281x DSP Boot ROM Reference Guide and the TMS320x281x DSP System Control and Interrupts Reference Guide for further

information.

Table 5-3. Reset (XRS) Timing Requirements(1)

MIN

NOM

MAX

UNIT

tw(RSL1)

Pulse duration, stable XCLKIN to XRS high

8tc(CI)

cycles

tw(RSL2)

Pulse duration, XRS low

Warm reset

8tc(CI)

cycles

tw(WDRS)

Pulse duration, reset pulse generated by

watchdog

512tc(CI)

cycles

td(EX)

Delay time, address/data valid after XRS

high

32tc(CI)

cycles

tOSCST

(2)

Oscillator start-up time

tsu(XPLLDIS)

Setup time for XPLLDIS pin

16tc(CI)

cycles

th(XPLLDIS)

Hold time for XPLLDIS pin

16tc(CI)

cycles

th(XMP/MC)

Hold time for XMP/MC pin

16tc(CI)

cycles

th(boot-mode)

Hold time for boot-mode pins

2520tc(CI)

(3)

cycles

TMS320F2810PBKA Datasheet(PDF) 33 Page - Texas Instruments

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