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TMS320F2810PBKA Datasheet(PDF) 83 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 173 page  CLKX FSX DX DR M54 M58 M56 M53 M55 M59 M57 LSB MSB M60 M61 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 83 TMS320F2810, TMS320F2811, TMS320F2812 www.ti.com SPRS174U – APRIL 2001 – REVISED JULY 2019 Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Specifications Copyright © 2001–2019, Texas Instruments Incorporated (1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. (2) 2P = 1/CLKG Table 5-55. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1)(2) NO. MASTER SLAVE UNIT MIN MAX MIN MAX M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns M61 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG Table 5-56. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) NO. PARAMETER MASTER SLAVE UNIT MIN MAX MIN MAX M53 th(CKXH-FXL) Hold time, FSX low after CLKX high P ns M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P ns M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high P + 6 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns Figure 5-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 |
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