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TMS320F2810PBKA Datasheet(PDF) 39 Page - Texas Instruments

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Part # TMS320F2810PBKA
Description  TMS320F281x Digital Signal Processors
PDF  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 39 Page - Texas Instruments

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XCLKOUT
(A)(B)
XCLKIN
(A)
C10
C3
C4
C9
C5
C8
C1
C6
39
TMS320F2810, TMS320F2811, TMS320F2812
www.ti.com
SPRS174U – APRIL 2001 – REVISED JULY 2019
Submit Documentation Feedback
Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812
Specifications
Copyright © 2001–2019, Texas Instruments Incorporated
(1)
A load of 40 pF is assumed for these parameters.
(2)
H = 0.5tc(XCO)
(3)
The PLL must be used for maximum frequency operation.
(4)
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
5.12.4.2.2 Output Clock Characteristics
Table 5-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
C1
tc(XCO)
Cycle time, XCLKOUT
6.67(3)
ns
C3
tf(XCO)
Fall time, XCLKOUT
2
ns
C4
tr(XCO)
Rise time, XCLKOUT
2
ns
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H – 2
H + 2
ns
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H – 2
H + 2
ns
C7
tp
PLL lock time(4)
131072tc(CI)
ns
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 5-11 is intended to illustrate the timing parameters only and may differ based on configuration.
B.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-11. Clock Timing



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