TMS320F2810PBKA datasheet(49/173 Pages) TI

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SPISOMI

SPISIMO

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

SPISTE

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Specifications

(1)

The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2)

tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

(3)

tc(LCO) = LSPCLK cycle time

(4)

Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5)

The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

5.12.5.5 Serial Peripheral Interface (SPI) Master Mode Timing

Table 5-22 lists the master mode timing (clock phase = 0) and Table 5-23 lists the master mode timing

(clock phase = 1). Figure 5-22 and Figure 5-23 show the timing waveforms.

Table 5-22. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)

NO.

PARAMETER

BRR EVEN

BRR ODD

UNIT

MIN

MAX

MIN

MAX

tc(SPC)M

Cycle time, SPICLK

4tc(LSPCLK)

128tc(LSPCLK)

5tc(LSPCLK)

127tc(LSPCLK)

tw(SPC1)M

Pulse duration, SPICLK first

pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M +

0.5tc(LSPCLK) – 10

0.5tc(SPC)M +

0.5tc(LSPCLK) + 10

tw(SPC2)M

Pulse duration, SPICLK second

pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M –

0.5tc(LSPCLK) – 10

0.5tc(SPC)M –

0.5tc(LSPCLK) + 10

td(SIMO)M

Delay time, SPICLK to

SPISIMO valid

tv(SIMO)M

Valid time, SPISIMO valid after

SPICLK

0.5tc(SPC)M – 10

0.5tc(SPC)M –

0.5tc(LSPCLK) – 10

tsu(SOMI)M

Setup time, SPISOMI before

SPICLK

th(SOMI)M

Hold time, SPISOMI valid after

SPICLK

td(SPC)M

Delay time, SPISTE active to

SPICLK

1.5tc(SPC)M –

3tc(SYSCLK) – 10

1.5tc(SPC)M –

3tc(SYSCLK) – 10

td(STE)M

Delay time, SPICLK to SPISTE

inactive

0.5tc(SPC)M – 10

0.5tc(SPC)M –

0.5tc(LSPCLK) – 10

Figure 5-22. SPI Master Mode External Timing (Clock Phase = 0)

TMS320F2810PBKA Datasheet(PDF) 49 Page - Texas Instruments

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