26HS01GTAM03 datasheet(26/166 Pages) INFINEON

26 / 166 page

Datasheet

26 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4Features

4.1

Error detection and correction

SEMPER™ Flash family devices support error detection and correction by generating an embedded hamming ECC

during memory array programming. This ECC code is then used for error detection and correction during read

operations. The ECC is based on a 16-byte data unit. When the 16-byte data unit is loaded into the Program Buffer

and is transferred to the 128-bits flash memory array Line for programming (after an erase), an 8-bit ECC for each

data unit is also programmed into a portion of the memory array that is not visible to the host system software.

This ECC information is then checked during each Flash array read operation. Any 1-bit error within the data unit

will be corrected by the ECC logic. The 16-byte data unit is the smallest program granularity on which ECC is

enabled.

When any amount of data is first programmed within a 16-byte data unit, the ECC value is set for the entire data

unit. If additional data is subsequently programmed into the same data unit, without an erase, then the ECC for

that data unit is disabled and the 1-bit ECC disable bit is set. A sector erase is needed to again enable ECC on that

data unit.

These are automatic operations transparent to the user. The transparency of the ECC feature enhances data

reliability for typical programming operations which write data once to each data unit while also facilitating

software compatibility with previous generations of products by still allowing for single-byte programming and

bit-walking (in this case, ECC will be disabled) in which the same data unit is programmed more than once.

Figure 19

16-Byte ECC data unit example

SEMPER™ NOR Flash supports 2-bit error detection as the default ECC configuration. In this configuration, any

1-bit error in a data unit is corrected and any 2-bit error is detected and reported. The 16-byte unit data requires

a 9-bit ECC for 2-bit error detection. When 2-bit error detection is enabled, byte-programming, bit-walking, or

multiple program operations to the same data unit (without an erase) are not allowed and will result in a Program

Error. Changing the ECC mode from 1-bit error detection to 2-bit error detection, or from 2-bit error detection to

1-bit error detection will invalidate all the ECC syndromes related to data in the memory array. When changing

the ECC mode, the host must first erase all sectors in the device. If the ECC mode is changed without erasing

programmed data, subsequent read operations will result in undefined behavior.

26HS01GTAM03 Datasheet(PDF) 26 Page - Infineon Technologies AG