26HS01GTAM03 datasheet(10/166 Pages) INFINEON

10 / 166 page

Datasheet

10 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

SEMPER™ Flash devices have built-in diagnostic features providing the host system with the device status.

• Program and erase operation: Reporting of program or erase success, failure and suspend statuses

• Error detection and correction: 1-bit and/or 2-bit error status with address trapping and error count

• Data integrity check: Error detection over memory array contents

• Interface CRC: Error detection over interface transactions

• SafeBoot: Reporting of proper flash device initialization and configuration corruption recovery

• Sector erase status: Reporting of erase success or failure status per sector

• Sector erase counter: Counts the number of erase cycles per sector

2.2

HYPERBUS™ transaction protocol

Transaction

All bus transactions can be classified as either read or write. A bus transaction is started with CS# going LOW with

CK = LOW and CK# = HIGH. The transaction to be performed is presented to the SEMPER™ Flash device during the

first three clock cycles in a DDR manner using all six clock edges. These first three clocks transfer three words of

Command / Address (CA0, CA1, CA2) information to define the transaction characteristics:

• Read or write transaction.

• Whether the transaction will be to the memory array or to register space.

- Although the HYPERBUS™ protocol provides for slave devices that have both memory and register address

spaces, SEMPER™ Flash memories described in this specification do not differentiate between memory and

registers as separate address spaces. There is a single address space selected by any transaction, independent

of whether the transaction indicates the target location is in memory space or register space. Write transac-

tions always place the transaction address and data into a command register set (buffer). Read transactions

returndatafrom thememoryarray orfromaregisteraddress spacewindowthathasbeen temporarilyoverlaid

within the single address space by the execution of commands. The single address space with register space

overlays methodology is backward compatible with legacy parallel NOR Flash devices.

• Whether a transaction will use a linear or wrapped burst sequence.

- Linearand wrapped burst are fully supported for readtransactions. SEMPER™ Flash also supports Hybrid burst

which combines one wrapped burst followed by linear burst.

- SEMPER™ Flash write transactions do not support burst sequence and ignore the burst type indication. Write

command transactions transfer a single word per write. Only the Word Program command write data transfer

may be done with a linear burst.

• The target half-page address (row and upper order column address).

• The target Word (within half-page) address (lower order column address).

Once the transaction has been defined, a number of idle clock cycles are used to satisfy any read latency require-

ments before data is transferred. Once the target data has been transferred the HYPERBUS™ master host

completes the transaction by driving CS# HIGH with CK = LOW and CK# = HIGH. Data is transferred as 16-bit values

with the first eight bits (15–8) transferred on a HIGH going CK (write data or CA bits) or DS edge (read data) and

the second eight bits (7–0) being transferred on the LOW going CK or DS edge. Data transfers during read or write

operations can be ended at any time by bringing CS# HIGH when CK = LOW and CK# = HIGH. Read data is edge

aligned with DS transitions and Write data is center aligned with clock edges.

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