26HS01GTAM03 datasheet(33/166 Pages) INFINEON

33 / 166 page

Datasheet

33 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.2.1

Configuration 1: Maximum endurance - single high endurance region

Maximum endurance is achieved when all 256KB sectors are designated as high endurance. All sectors must be

designated as high endurance using the Infineon Endurance Flex pointer architecture. Maximum endurance

pointer configuration is shown in Table 16.

4.2.2

Configuration 2: Two region selection - one long retention region and

one high endurance region

Sectors for long retention or high endurance must be delineated using the Infineon Endurance Flex pointer

architecture. Region 0 is defined as long retention and consists of 16 sectors. Region 1 is defined as high

endurance and has 240 sectors. The pointer setup for two region configuration is shown in Table 17.

4.2.3

HYPERBUS™ Endurance Flex related registers and transaction

4.2.4

Legacy (x1) SPI Endurance Flex related registers and transaction

Table 16

Endurance Flex pointer values for maximum endurance configuration[16]

Pointer #

Pointer address

EPTADn[8:0]

Region type

ERGNTn

Pointer enable#

EPTEBn

Global region selection

GBLSEL

Wear leveling enable

WRLVEN

N/A

1’b1

9’b111111111

1’b1

N/A

9’b111111111

Table 17

EnduraFlex pointer values for two region configuration[17]

Pointer #

Pointer address

EPTADn[8:0]

Region type

ERGNTn

Pointer enable#

EPTEBn

Global region selection

GBLSEL

Wear leveling enable

WRLVEN

N/A

1’b0

1’b1

9’b000010000

1’b1

1’b0

N/A

Table 18

HYPERBUS™ Endurance Flex related registers and transactions

Related registers (see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions (see Table 120 on page 124)

Infineon Endurance Flex architecture selection registers (EFX4O, EFX3O,

EFX2O, EFX1O, EFX0O)

Read EnduraFlex Registers (RDOENX_1_1) - EnduraFlex ASO

Program EnduraFlex Registers (PGOENX_2_1) - EnduraFlex ASO

Table 19

Legacy (x1) SPI Endurance Flex related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

Infineon Endurance Flex architecture selection registers (EFX4O, EFX3O,

EFX2O, EFX1O, EFX0O)

Read Any Register (RDARG_4_0)

Write Any Register (WRARG_C_1)

Notes

16. This is also the default configuration of the device.

17. The number of pointers defined is based on the number of regions configured.

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