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26HS01GTAM03 Datasheet(PDF) 82 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 82 Page - Infineon Technologies AG |
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82 / 166 page ![]() Datasheet 82 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Features 4.15 Reset HL-T/HS-T devices support four types of reset mechanisms. • Hardware Reset (Using RESET# input pin) •Power-On Reset (POR) • CS# Signaling Reset • Software Reset - SPI Only 4.15.1 Hardware reset (Using RESET# input pin) The RESET# input initiates the reset operation with a transition from logic High to logic Low for > tRP, and causes the device to perform the full reset process that is performed during POR. The hardware reset process requires a period of tRH to complete. See Table 129 for timing specifications. Figure 39 Hardware reset using RESET# input (Reset pulse = tRP(Min)) Figure 40 Hardware reset using RESET# input (Reset pulse > (tRP + tRH)) Figure 41 Hardware reset using RESET# input (Back to back hardware reset) Table 61 Erase error (ERSERR) summary Error Flag Symbol Conditions Erase Error ERSERR Sector Device Erase - All bits cannot be erased to ‘1’s Trying to erase a protected region Register Erase - All bits cannot be erased to ‘1’s during Erase portion of Register Write SafeBoot Failure |
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