26HS01GTAM03 datasheet(12/166 Pages) INFINEON

12 / 166 page

Datasheet

12 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

Figure 3

Read operation (Single initial latency)[4, 5, 6, 7, 8]

Write operations

A write operation starts with the first three clock cycles providing the CAx (Command / Address) information

indicating the transaction characteristics. The Burst Type bit CA[45] is “don’t care” because the SEMPER™ Flash

device only supports a single write transaction of 16-bit or a continuous linear write burst that is only supported

when loading data during a Word Program command. Immediately following the CA information the host is able

to transfer the write data on the DQ bus. The first byte (A) of data is presented on the rising edge of CK and the

second byte (B) is presented on the falling edge of CK. Write data is center aligned with the CK/CK# inputs. Write

transfers can be ended at any time by bringing CS# HIGH when CK = LOW and CK# = HIGH.

Figure 4

Write operation[4, 9, 10]

Notes

4. Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new transaction is initiated.

5. Read access from the flash array starts once CA[23:16] is captured.

6. The read latency is defined by the Read Latency value in the Volatile Configuration Register (or the Nonvolatile Configuration Register).

7. In this example of a read operation, the Latency Count was set to four clocks.

8. Data out during a Register Read transaction is only valid during the first word output by the device. Subsequent data values output if CK/CK# continue

to toggle while CS# remains LOW are undefined.

9. DS will be driven Low as long as CS# is LOW but is not used during Write transactions.

10. Write operations are limited to a transaction of a single word (16-bit) or a linear write burst supported only when loading data during a Word Program

command.

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