26HS01GTAM03 datasheet(84/166 Pages) INFINEON

84 / 166 page

Datasheet

84 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

This reset sequence is not intended to be used at normal power on, but to be used only when the device is not

responding to the system. This reset sequence will be operational from any state that the device may be in.

Hence, CS# signaling reset is useful for packages that don't support a RESET# pin to provide behavior identical

to Hardware Reset.

Figure 44

CS# signaling reset protocol

4.15.4

Software reset - SPI only

Software controlled Reset transaction restores the device to its initial power up state, by reloading Volatile

registers from nonvolatile default values except the protection registers. A reset transaction (SFRST_0_0) is

executed when CS# is brought HIGH at the end of the transaction and requires tSRtime to execute. See Table 129

for timing specifications.

The Reset Enable (SRSTE_0_0) transaction is required immediately before a Reset transaction (SFRST_0_0) such

that a software reset is a sequence of the two transactions. Any transaction other than SFRST_0_0 following the

SRSTE_0_0 transaction will clear the reset enable condition and prevent a later SFRST_0_0 transaction from

being recognized.

The Reset (SFRST_0_0) transaction immediately following a SRSTE_0_0 transaction, initiates the software reset

process. During software reset, only RDSR1_4_0 and RDARG_4_0 of Status Register 1 are supported operations

as long as the volatile and nonvolatile configuration states of the device are the same. if the configuration state

is changing during software reset, reading Status Register 1 should only be done after the software reset time has

elapsed.

The software reset is independent of the state of RESET#. If RESET# is HIGH or Unconnected, and the software

reset transactions are issued, the device will perform software reset.

4.15.4.1

Software reset related registers and transactions

Table 62

Software reset related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

N/A

Software Reset Enable (SRSTE_0_0)

Software Reset (SFRST_0_0)

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