26HS01GTAM03 datasheet(30/166 Pages) INFINEON

30 / 166 page

Datasheet

30 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.1.1.4

INT# output - HYPERBUS™ only

• SEMPER™ Flash supports INT# output pin to indicate to the host system that an event has occurred within the

flash device. The user can configure the INT# output pin to transition to the active (Low) state when:

- 2-bit ECC error is detected

- 1-bit ECC error is detected

- Transitioning from the Busy to the Ready state

The INT# pin is only available in BGA package. Operation is controlled with the Interrupt Configuration Register

(INCV) where the INT# output (normally High) is enabled. The Interrupt Configuration Register determines

when an internal event is enabled to trigger a High to Low transition on the INT# output pin.

The Interrupt Status Register (INSV) indicates what enabled internal event(s) have occurred since the last time

the INSV was cleared.

If enabled, the INT# output pin will then transition from High to Low upon the occurrence of an enabled event.

Once the host recognizes that INT# has transitioned to the Low state the INSV Register can be read to deter-

mine which internal event was responsible.

INT# output status during POR, Hardware Reset, Software Reset, DPD Exit, or CS# Signaling Reset is not valid.

• The INCV and INSV can be accessed through Program/Read INCV/INSV HYPERBUS™ transactions.

• The INT# output can be forced to transition back to the High state (returned High by an external pull-up resis-

tance) using the following methods:

- Disable the INT# output by loading a ‘1’ into bit 15 of the Interrupt Configuration Register.

- Reset the appropriate bit (by writing a ‘1’) in the INSV bit that indicates which internal event occurred to cause

the output to go Low. All INSV bits that are Low and are also enabled in the INSV must be reset before the INT#

output will return HIGH.

- If the internal event is ECC, then issuing Clear ECC Errors transaction while in the ECC ASO will return INT#

output HIGH. Clear ECC Errors clears INSV ECC related bits (INSV[1:0]) but does not disable INCV.

- TheINT#outputwillalsobereturnedtothedefault(disabled,High-Z)statewithCS#SignalingReset,Hardware

Reset (RESET# = Low) or a POR. Hardware Reset and POR disable all interrupts by setting the Interrupt

Configuration Register back to the default (all interrupts disabled) state.

4.1.2

HYPERBUS™ ECC related registers and transactions

4.1.3

Legacy (x1) SPI ECC related registers and transactions

Table 13

HYPERBUS™ ECC related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

Configuration Register - 2 (CFR2N, CFR2V)

Read Configuration Register 2 (RDVCR2_4_0, RDNCR2_4_0)

ECC Address Trap Register (EATV)

Read Address Trap Register (RDADTU_2_1, RDADTL_2_1) - ECC ASO

ECC Error Detection Counter Register (ECTV)

Read ECC Count Value Register (RDCONT_2_1) - ECC ASO

INT# Pin Configuration Register (INCV)

Read Interrupt Configuration Register (RDVINC_4_0)

INT# Pin Status Register (INSV)

Read Interrupt Status Register (RDVINS_4_0)

Program Interrupt Configuration Register (PGVINC_4_0)

Program Interrupt Status Register (PGVINC_4_0)

Table 14

Legacy (x1) SPI ECC related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

Configuration Register - 2 (CFR2N, CFR2V)

Read Any Register (RDARG_4_0)

ECC Address Trap Register (EATV)

Write Any Register (WRARG_C_1)

ECC Error Detection Counter Register (ECTV)

Read ECC Status (RDECC_4_0)

26HS01GTAM03 Datasheet(PDF) 30 Page - Infineon Technologies AG

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