26HS01GTAM03 datasheet(13/166 Pages) INFINEON

13 / 166 page

Datasheet

13 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

2.3

Legacy (x1) SPI transaction protocol

Transaction

• During the time that CS# is active (Low) the clock signal (CK) is toggled while command information is first

transferred on the data input (SI/DQ0) signal followed by address and data from the host to the flash device.

The clock continues to toggle during the transfer of read data from the flash device to the host (SO/DQ1) or write

data from the host to the flash device (SI/DQ0). When the host has transferred the desired amount of data, the

host drives the CS# inactive (High). The period during which CS# is active is called a transaction on the bus.

• While CS# is inactive, the CK is not required to toggle.

• The command transfer occurs at the beginning of every transaction. The address, latency cycles, and data

transfer phases are optional and their presence depends on the protocol mode or command transferred.

Transaction capture

• CK marks the transfer of each bit or group of bits between the host and memory. Command, address and write

data bits transfer occurs on CK rising edge.

Note All attempts to read the flash memory array during a program or erase (embedded operations) are ignored.

The embedded operation will continue to execute without any effect. A very limited set of commands are

accepted during an embedded operation. These are discussed in Suspend and resume embedded operation

on page 76.

Protocol

• The legacy (x1) SPI mode is the default protocol following Power-on-Reset (POR) but, flash devices can be

configured to boot-up in the HYPERBUS™ mode.

• Each transaction begins with an 8-bit (1-byte) command. The command selects the type of information transfer

or device operation to be performed.

• This protocol uses SI/DQ[0] to transfer information from host to flash device and SO/DQ[1] to transfer infor-

mation from flash device to host. On each DQ, information is placed on the DQ line in Most Significant bit (MSb)

to least significant bit (LSb) order within each byte. Sequential address bytes are transferred in highest order

to lowest order sequence. Sequential data bytes are transferred in lowest address to highest address order.

• DQ[7:2] are not used for data transfer period. Hence, the DQ[7:2] signals will be high impedance.

2.3.1

Transaction details

Figure 5

SPI transaction with command input

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