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26HS01GTAM03 Datasheet(PDF) 100 Page - Infineon Technologies AG

Part # 26HS01GTAM03
Description  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 100 Page - Infineon Technologies AG

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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Registers
5.2.12
AutoBoot register (ATBN) (x8)
The AutoBoot Register (ATBN) provides a means to automatically read boot code as part of the power-on reset,
or hardware reset process.
5.2.13
POR time register (PORT) (x8)
The POR Time register contain the count by which the RSTO# period is extended beyond POR period.
5.2.14
Sector erase count register (SECV) (x8)
The Sector Erase Count Register (SECV) contains the number of times the addressed sector has been erased.
Table 79
AutoBoot register (x8)
Bit number
Name
Function
Read/write
N = Nonvolatile
V = Volatile
Factory
default
(binary)
Description
ATBN[31:9]
STADR[22:0]
Starting Address Selection
where AutoBoot will start
reading data from
N => R/W
0000000000
0000000000
000
Description: The STADR[22:0] bits set the starting
address from which the device will output the read data.
Selection Options: Address Bits
Dependency: N/A
ATBN[8:1]
STDLY[7:0]
AutoBoot Read Starting
Delay Selection
N => R/W
00000000
The STDLY[7:0] bits specify the initial delay (clock cycles)
needed by the host before it can accept data.
Note STDLY[7:0]=0x00 is valid for SPI up to 50MHz.
STDLY[8:1]=0x01 or higher is valid for SPI/DPI/QPI up to
166MHz. STDLY[7:0] = 0x05 or higher is valid for
OPI/HYPERFLASH™ up to 200MHz.
Selection Options: Address Bits
Dependency: N/A
ATBN[0]
ATBTEN
AutoBoot Feature
Selection
N => R/W
0
Description: The ATBTEN bit enables or disables the
AutoBoot feature.
Selection Options:
0 = AutoBoot feature disabled
1 = AutoBoot feature enabled
Dependency: N/A
Table 80
POR time register (x8)
Non-Volatile-Memory Core Bits
Description
Bits
Name
Function
Read/write
Default
state
15:0
PORT_NV
Power-On-Reset Time
R/W
FFFFh
To extend the RSTO# period beyond the POR period, the
non-volatile POR Time Register must be programmed.
0000000000000000b
...............................
1111111111111111b
Table 81
Sector erase count register (x8)
Bit number
Name
Function
Read/write
N = Nonvolatile
V = Volatile
Factory
default
(binary)
Description
SECV[31:24]
RESVRD
Reserved for Future Use
V => R
11111111
This bit is Reserved for future use. This bit must always
be written/loaded to its default state.



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