26HS01GTAM03 datasheet(11/166 Pages) INFINEON

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Datasheet

11 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

Transaction capture

CK/CK# mark the transfer of each bit or group of bits between the host and memory. Command, address and write

data bits transfer occurs on CK edges or CK/CK# crossing.

Note All attempts to read the flash memory array during a program or erase (embedded operations) are ignored.

The embedded operation will continue to execute without any effect. A very limited set of commands are

accepted during an embedded operation.

Read

CA0 indicates that a read operation is to be performed and also indicates the burst type (wrapped or linear). Read

operations begin the internal array access as soon as the half-page address has been presented in CA0 and CA1.

CA2 identifies the target word address within the chosen half-page. The host then continues clocking for a

number of cycles defined by the latency count setting in the Configuration Register. Once these latency clocks

have been completed the memory starts to simultaneously transition the Data Strobe (DS) and begins outputting

the target data. New data is output in an edge aligned fashion upon every transition of DS. Data will continue to

be output as long as the host continues to transition the clock (CK and CK#). Wrapped bursts will continue to wrap

within the burst length and linear burst will output data in a sequential manner across page boundaries. A Hybrid

Burst provides one initial wrapped burst followed by linear burst, as described in Burst types on page 57.

Wrapped reads can be performed from the main array, the SFDP Tables and the Secure Silicon Region (SSR). Read

transfers can be ended at any time by bringing CS# High when CK = Low and CK# = High.

When a linear burst reaches the last address in the array, if the burst continues, the address counter will wrap

around and roll back to address 000000h, allowing the read sequence to be continued indefinitely.The entire

memory can therefore be read out with one single read instruction.

The 16-byte and 32-byte wrapped bursts do not cross page boundaries and do not incur inter-page boundary

crossing latencies. For a 64-byte wrapped burst read, a latency may occur during the target address to next page

boundary crossing, depending on the starting address (see Table 48).

Inter-page boundary latency can be avoided by choosing double initial latency CFR2x[7] option. This allows the

device to fetch two consecutive pages during each access allowing latency free data access.

Table 2

Command / Address bit assignment

CA bit#

Bit name

Bit function

R/W#

Identifies the transaction as a Read or Write.

1 = Read operation

0 = Write operation

Target space is defined in CA46.

Target

Indicates whether the Read or Write operation accesses the memory or register spaces.

0 = Memory space

1 = Register space

The register space is intended to be used by volatile memory and peripheral devices. The HYPERFLASH™

devices will not take advantage of this feature and this bit should be set to 0 during Read or Write trans-

actions.

Burst Type

Indicates whether the burst will be linear or wrapped.

0 = Wrapped burst

1 = Linear burst

44–39 (1Gb)

44–38 (512Mb)

44–37 (256Mb)

Reserved

Reserved for future address expansion.

Reserved bits should be set to 0 by the host controller.

38–16 (1Gb)

37–16 (512Mb)

36–16 (256Mb)

Row and Upper Column

Address

Half page component of target address.

15–3

Reserved

Reserved for future column address expansion.

Reserved bits should be set to 0 by the host controller.

2–0

Lower Column Address Lower Column component of the target address: System word address bits A2–0 selecting the starting

word within a half-page.

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