26HS01GTAM03 datasheet(36/166 Pages) INFINEON

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Datasheet

36 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

The host device will read the CRC checksum from the slave device using the Read Interface CRC transaction. The

slave device will include the RDCRC_4_0 transaction as part of the CRC checksum and then place the checksum

data on the data bus. If the host device upon receiving the slave’s CRC checksum finds a mismatch with its own

calculated CRC checksum, it can re-issue the Program / Erase transaction to the slave device. For Flash, multiple

Program / Erase to the same location due to CRC checksum errors will affect data endurance.

4.3.3

HYPERBUS™ interface CRC related registers and transaction

4.3.4

Legacy (x1) SPI interface CRC related registers and transaction

4.4

Data integrity CRC

HL-T/HS-T family devices have a group of transactions to perform a hardware accelerated CRC calculation over

a user defined address range in the memory array. The calculation is another type of embedded operation similar

to programming or erase, in which the device is busy while the calculation is in progress. The CRC operation uses

the same CRC32 polynomial as Interface CRC to determine the CRC check-value.

CRC32 Polynomial: X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1

The check-value generation sequence is started by entering the Data Integrity Check (DICHK_4_1, LDENAD_1_1)

transaction. The transaction includes/requires loading the beginning address into the CRC Start Address

Bringing CS# HIGH starts the CRC calculation. The CRC process calculates the check-value on the data contained

at the starting address through the ending address. Note that in HYPERBUS™ interface, loading the ending

address initiates the Data Integrity CRC calculation.

During the calculation period, the device goes into the Busy state (RDYBSY = 1). Once the check-value calculation

is completed, the device returns to the Ready state (RDYBSY = 0) and the calculated check-value is available to

be read. The check-value is stored in the Data Integrity CRC Register (DCRV[31:0]) and can be read (RDARG_4_0,

RDDICL_2_1, RDDICU_2_1).

The check-value calculation can only be initiated when the device is in Standby State; and once started it can be

suspended with the CRC Suspend transaction (SPEPD_0_0, SP_DIC_1_1) to read data from the memory array.

During the Suspended state, the CRC Suspend Status Bit in the Status Register will be set (DICRCS = 1). Once

suspended, the host can read the Status Register, read data from the array and can resume the CRC calculation

by using the CRC Resume transaction (RSEPS_0_0, RS_DIC_1_1).

The Ending Address (ENDADD) must be at least two addresses higher than the Starting Address (STRADD). If

ENDADD < STRADD + 3 the check-value calculation will abort and the device will return to the Ready state (RDYBSY

= 0). In Legacy (x1) SPI, Data Integrity CRC abort status bit will be set (DICRCA = 1) to indicate the aborted

condition. The DICRCA bit can be cleared, once set, by Software Reset or a valid subsequent CRC command

execution. In HYPERBUS™, Write Buffer Abort bit will be set (WRBFAB = 1) to indicate the aborted condition. A

Status Register Clear will clear the WRBFAB bit and allow a subsequent valid CRC command or CRC ASO exit

sequence. If ENDADD < STRADD + 3, the check-value will hold indeterminate data.

The read data ordering used in calculating the check-value from the CRC-32 polynomial is shown as follows:

Table 20

HYPERBUS™ interface CRC related registers and transactions

Related registers (see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions (see Table 120 on page 124)

N/A

Read Interface CRC Register (RDICRC_1_1) - Read Interface ASO

Table 21

Legacy (x1) SPI interface CRC related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

Interface CRC Enable Register (ICEV)

N/A

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