26HS01GTAM03 datasheet(70/166 Pages) INFINEON

70 / 166 page

Datasheet

70 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.10.1.8

Program persistent protection bits (PPB)

The Program Persistent Protect Bits (PGNPPB_2_1) transaction programs a bit in the PPB Register to protect the

addressed sector from being programed or erased.

The PRGERR bit in STRV[4] may be checked to determine if any error occurred during the operation. Program PPB

bit transaction will abort when trying to program the PPB bits protected by PPBLCK (PPLV[0]) bit.

4.10.1.9

Clear ECC status register transaction

The Clear ECC Status Register (CLRECC_1_1) transaction resets bit ECSV[4] (2-bit ECC Detection), bit ECSV[3]

(1-bit ECC Correction), INSV[1:0] ECC detection status bits.

4.10.1.10 Clear PPB lock bit

The Clear PPB Lock Bit (CLVPPL_2_1) transaction clears the PPB Lock Register PPLV[0] to 0. The PPBLCK bit is

used to protect the PPB bits. When PPLV[0] = 0, the PPB Program/Erase transaction will be aborted.

4.10.2

Legacy (x1) SPI

In SPI, before any program transaction can be accepted by the device, a Write Enable (WRENB_0_0) transaction

must be issued which sets the Write/Program Enable (WRPGEN) bit in Status Register 1 to enable program opera-

tions. When a program transaction is completed, the WRPGEN bit is reset to a ‘0’.

While the program transaction is in progress, the Status Register may be read to check the value of the Device

Ready/Busy (RDYBSY) bit. The RDYBSY bit is a ‘1’ during the self-timed program transaction, and is a ‘0’ when it is

completed.

The PGMERR bit may be checked to determine if any error occurred during the program transaction.

A program transaction applied to a sector that has been Write Protected through any of the protection schemes,

will not be executed and will set the PGMERR status fail bit.

4.10.2.1

Program granularity

The HS/L-T family supports multi-pass programming (bit walking) where programming a “0” over a “1” without

performing the sector erase operation. Bit-walking is allowed for the non-AEC-Q100 industrial temperature range

(40°C to +85°C) of this device. It is required to perform only one programming operation (single-pass

programming) on each ECC data unit between erase operations for the higher temperature range (40°C to

+105°C) and (40°C to +125°C) devices and all AEC-Q100 devices.

Multi-pass programming without an erase operation will disable the device’s ECC functionality for that data unit.

Note that if 2-bit ECC is enabled, multi-pass Programming within the same sector will result in a Program Error.

4.10.2.2

Page programming

Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming

command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that

can be programmed with a single programming transaction. Page Programming allows up to a page size (either

256- or 512-bytes) to be programmed in one operation. The page size is determined by the Configuration Register

3 bit CFR3V[4]. The page is aligned on the page size address boundary. It is possible to program from one bit up

to a page size in each Page Programming operation. It is recommended that a multiple of 16-byte length and

aligned Program Blocks be written. This ensures that ECC is not disabled. For the very best Page Program

throughput, programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each

Page being programmed only once.

4.10.2.3

Program page transaction

The Program Page transaction (PRPGE_4_1) programs data into the memory array. If data more than a page size

(256B or 512B) is sent to the device, then the space between the starting address and the page aligned end

boundary, the data loading sequence will wrap from the last byte in the page to the zero byte location of the same

page and begin overwriting any data previously loaded in the page. If less than a page of data is sent to the device,

then the sent data bytes will be programmed in sequence, starting at the provided address within the page,

without having any effect on the other bytes of the same page. The programming process is managed by the

device internal control logic. The PRGERR bit indicates if an error has occurred in the programming transaction

that prevents successful completion of programming. This includes attempted programming of a protected area

(see Transaction table on page 124).

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