26HS01GTAM03 datasheet(91/166 Pages) INFINEON

91 / 166 page

Datasheet

91 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

CFR1N[10]

CFR1V[10]

TLSSRP

Temporary Locking

selection of Secure

Silicon Region

N => R/W

V => R/W

Description:

The TLSSRP bit temporarily protects the SSR. Upon power-up

or a hardware reset, TLSSRP is set to its default state. When

selected, it protects the SSR from programming.

Selection Options:

0 = Secure Silicon Region is protected

1 = Secure Silicon Region is not protected

Dependency: N/A

CFR1N[9:8]

CFR1V[9:8]

TB4KBS[1:0]

Top or Bottom

Address Range

Selection for 4KB

Sector Block

N => R/W

V => R/W

Description:

The TB4KBS bits define the logical address location of the 4KB

sector block. The 4KB sector block replaces the fitting portion

of the highest or lowest address sector.

Selection Options:

00 = 4KB Sector Block and Read Password Sector is mapped

into the bottom of the memory address space

01 = 4KB Sector Block and Read Password Sector is mapped

into the top of the memory address space

10 = Uniform Sector architecture and Read Password Sector

is mapped into the bottom of the memory address space

11 = Uniform Sector architecture and Read Password Sector

is mapped into the top of the memory address space

Dependency: N/A

CFR1N[7:4]

CFR1V[7:4]

MEMLAT[3:0]

Memory Array Read

Latency selection -

Dummy cycles

required for initial

data access

N => R/W

V => R/W

1011

Description:

The MEMLAT[3:0] bits control the read latency (dummy

cycles) delay in all variable latency memory array and Nonvol-

atile Register read transactions. MEMLAT selection allows the

user to adjust the read latency during normal operation based

on different operating frequencies. The device will support 20

cycles read latency upon erasing the configuration register - 1.

Selection Options:

0000 = 5 Latency Cycles Selection based on transaction

opcodes

…..

1100 = 20 Latency Cycles Selection based on transaction

opcodes

Dependency: N/A

CFR5V[3]

RESVRD

Reserved for Future

Use

N => R/W

V => R/W

These bits are Reserved for future use. This bit must always be

written/loaded to its default state.

CFR1N[2]

CFR1V[2]

DTSTSL

Data Strobe Stall

during Device Error

Selection (DS)

N => R/W

V => R/W

Description:

The DTSTSL bit selects whether Data Strobe (DS) stalls on

device errors such as 2-bit ECC detection.

Selection Options:

0 = DS stalls on device errors

1 = DS does not stall on device errors

Dependency: N/A

CFR1N[1:0]

CFR1V[1:0]

RBSTWL[1:0] Read Burst Wrap

Length selection

N => R/W

V => R/W

Description:

The RBSTWL[1:0] bits select the read burst wrap length and

alignment during normal operation. It selects the fixed

length/aligned group of 16, 32, or 64 bytes.

Selection Options:

00 = Reserved

01 = 64 Bytes Wrap length

10 = 16 Bytes Wrap length

11 = 32 Bytes Wrap length

Dependency: N/A

Table 67

Configuration register 1 (x8) (Continued)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

26HS01GTAM03 Datasheet(PDF) 91 Page - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 91 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL