26HS01GTAM03 datasheet(94/166 Pages) INFINEON

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Datasheet

94 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.2.3

Status registers (x8)

Status Register provides device status on operation.

Table 70

Status register (x8)[24]

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

STRV[15:9]

RESVRD

Reserved for Future Use

V => R

1111111

This bit is Reserved for future use. This bit must always be

written/loaded to its default state.

STRV[8]

DICRCS

Memory Array Data

Integrity Check CRC

Suspend Status Flag

V => R

Description:

The DICRCS bit is used to determine when the device is in

Memory Array Data Integrity Check CRC suspend mode.

Selection Options:

0 = Memory Array Data Integrity Check CRC is not in suspend

mode

1 = Memory Array Data Integrity Check CRC is in suspend

mode

Dependency: N/A

STRV[7]

RDYBSY

Device Ready/Busy

Status Flag

V => R

Description:

The RDYBSY bit indicates whether the device is performing an

embedded operation or is in standby mode ready to receive

new operation transactions.

Note If PRGERR or ERSERR is set, the RDYBSY bit will set to a

‘1’.

Selection Options:

0 = Device is busy and unable to receive new operation trans-

actions

1 = Device is in standby mode ready to receive new operation

transactions (Host needs to check PRGERR and ERSERR

before providing a new transaction)

Dependency: N/A

STRV[6]

ERASES

Erase operation

Suspend Status Flag

V => R

Description:

The ERASES bit is used to indicate if the Erase operation is

suspended.

Selection Options:

0 = Erase operation is not in suspend mode

1 = Erase operation is in suspend mode

Dependency: N/A

STRV[5]

ERSERR

Erasing Error Status

Flag

V => R

Description:

The ERSERR bit indicates erase operation success or failure.

When the ERSERR bit is set to a ‘1’, it indicates that there was

an error in the last erasing operation. ERSERR bit is also set

when a erase operation is attempted within a protected

memory sector. When ERSERR is set, it can only be cleared

with the Clear Status Register (CLSR) transaction or a

hardware/software reset.

Note The device will only go to standby mode once the

ERSERR flag is cleared.

Selection Options:

0 = Last erase operation was successful

1 = Last erase operation was unsuccessful

Dependency: N/A

STRV[4]

PRGERR

Programming Error

Status Flag

V => R

Description:

The PRGERR bit indicates program operation success or

failure. When the PRGERR bit is set to a ‘1’, it indicates that

there was an error in the last programming operation.

PRGERR bit is also set when a program operation is

attempted within a protected memory region. When PRGERR

is set, it can only be cleared with the Clear Status Register

(CLSR) transaction or a hardware/software reset.

Note The device will only go to standby mode once the

PRGERR flag is cleared.

Selection Options:

0 = Last programming operation was successful

1 = Last programming operation was unsuccessful

Dependency: N/A

Note

24. STRV value during POR, Hardware Reset, DPD Exit, and CS# Signaling Reset is not valid.

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