26HS01GTAM03 datasheet(72/166 Pages) INFINEON

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Datasheet

72 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.11

Erase

There are erase transactions for erasing data bits to 1 (all bytes are FFh). These program transactions can use any

of these two protocols:

• Legacy (x1) SPI interface with SDR - Erase the Memory Array and Persistent Protection Bits.

• HYPERBUS™ interface with DDR - Erase Registers, the Memory Array and Persistent Protection Bits.

• When the device is shipped from the factory the default erase state is all bytes are FFh.

4.11.1

HYPERBUS™

4.11.1.1

Chip erase

The Chip Erase function erases the entire Flash Memory Array. The device does not require the system to

preprogram prior to erase. The Embedded Erase Algorithm automatically programs and verifies the entire

memory for an all 0 data pattern prior to electrical erase. After a successful Chip Erase, all locations within the

device contain FFFFh. The system is not required to provide any controls or timings during these operations. The

Chip Erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the Chip Erase command, which in turn invokes the

Embedded Erase Algorithm.

When the Embedded Erase Algorithm is complete, the EAC returns to the Standby state. Note that while the

Embedded Erase operation is in progress, the system cannot read valid data from the array. The system can

determine the status of the erase operation by reading the Status Register. See Error types and reporting -

HYPERBUS™ on page 80 for information on these status bits. Once the Chip Erase operation has begun, only a

Status Read, Hardware Reset, or Power cycle are valid. All other commands are ignored. However, a Hardware

Reset or Power Cycle immediately terminates the erase operation and returns to Read mode after tRPH time. If a

chip erase operation is terminated, the Chip Erase command sequence must be reinitiated once the device has

returned to the Standby state to ensure data integrity.

Sectors protected by the ASP DYB and PPB bits will not be erased. If a sector is protected during Chip Erase, Chip

Erase will skip the protected sector and continue with next sector erase. The Status Register Erase Status Bit and

Sector Lock Bit are not set to 1 by a failed erase on a protected sector.

Note that Chip Erase cannot be suspended.

4.11.2

Sector erase

The Sector Erase function erases one sector in the memory array. The device does not require the system to

preprogram prior to erase. The Embedded Erase Algorithm automatically programs and verifies the entire sector

for an all 0 data pattern prior to electrical erase. After a successful sector erase, all locations within the erased

sector contain FFFFh. The system is not required to provide any controls or timings during these operations. The

Sector Erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the address of the sector to be erased, and the Sector Erase

command.

The system can determine the status of the erase operation by reading the Status Register.

Once the sector erase operation has begun, the Status Register Read and Erase Suspend commands are valid. All

other commands are ignored by the Embedded Algorithm Controller. However, note that a Hardware Reset

immediately terminates the erase operation and returns to Read mode after tRPH time. If a sector erase operation

is terminated, the Sector Erase command sequence must be reinitiated once the device has reset operation to

ensure data integrity. See Embedded algorithm controller (EAC) on page 16.

Sectors protected by the ASP DYB and PPB bits will not be erased. If an erase operation is attempted to a locked

sector the operation will be aborted and the failure will be indicated in the Status Register.

26HS01GTAM03 Datasheet(PDF) 72 Page - Infineon Technologies AG

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