26HS01GTAM03 datasheet(55/166 Pages) INFINEON

55 / 166 page

Datasheet

55 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.8.3.2

Read any register - Legacy (x1) SPI

The Read Any Register (RDARG_4_0) transaction is the best way to read all device registers, both Nonvolatile and

Volatile. The transaction includes the address of the register to be read. This is followed by a number of latency

cycles set by (CFR2V[3:0]) for reading Nonvolatile registers and CFR3V[7:6] for reading Volatile registers. Then, the

selected register contents are returned. If the read access is continued, the same addressed register contents are

returned until the transaction is terminated; only one byte register location is read by each RDARG_4_0 trans-

action. For registers with more that one byte of data, the RDARG_4_0 transaction must be repeated with the

address of the second byte (and so on) to read each byte of data.

The maximum clock frequency for the RDARG_4_0 transaction is 166MHz under SPI mode.

The RDARG_4_0 transaction can be used during embedded operations to read Status Register 1 (STR1V). It is not

used for reading registers such as ASP PPB Access Register (PPAV) and ASP Dynamic Block Access Register (DYAV).

There are separate commands required to select and read the location in the array accessed. The RDARG_4_0

transaction will read invalid data from the PASS Register locations if the ASP Password protection mode is

selected by programming ASPR[2:0]. Reading undefined locations provides undefined data.

4.8.3.3

Read status registers transaction

The Read Status Register (RDSR1_0_0, RDSR2_0_0, RDVSTR_2_0) transactions allow the registers’ volatile

contents to be read. The SPI mode has no address cycles. The SPI transaction uses latency cycles set by

(CFR3V[7:6]) for reading Volatile registers to enable maximum clock frequency of 166MHz. The HYPERBUS™ trans-

action uses latency cycles set by (CFR1V[7:4]) for reading Volatile registers to enable maximum clock frequency

of 166MHz under HL-T, and 200MHz under HS-T. The HYPERBUS™ mode supports DS for capturing data.

The Status Register (SPI - volatile only) contents can be read at any time, even while a program, erase, or write

operation is in progress.

In SPI mode, it is possible to continuously read Status Register by providing multiples of eight clock cycles. The

status is updated for each eight cycle read.

4.8.3.4

Read dynamic protection bit (DYB) access register transaction

The Read DYB Access Register (RDDYB_4_0, RDVDYB_1_1) transaction reads the contents of the DYB Access

maximum clock frequency of 166MHz. The HYPERBUS™ transaction uses latency cycles set by (CFR1V[7:4]) for

reading Volatile registers to enable maximum clock frequency of 166MHz under HL-T, and 200MHz under HS-T.

The HYPERBUS™ mode supports the DS for capturing data. It is not possible to read DYB Access Register contin-

uously for the entire array. Each location must be read with a separate Read DYB transaction.

4.8.3.5

Read persistent protection bit (PPB) access register transaction

The Read PPB Access Register (RDPBB_4_0, RDNPPB_1_1) transaction reads the contents of the PPB Access

maximum clock frequency of 166MHz. The HYPERBUS™ transaction uses latency cycles set by (CFR1V[7:4]) for

reading Volatile registers to enable maximum clock frequency of 166MHz under HL-T, and 200MHz under HS-T.

The HYPERBUS™ mode supports the DS for capturing data. It is not possible to read PPB Access Register contin-

uously for all the sectors in the array. Each location must be read with a separate Read PPB transaction.

4.8.3.6

Read PPB lock transaction

The Read PPB Lock Register (RDPLB_0_0, RDVPPL_1_1) transaction allows reading the global Persistent

Protection Lock bit. The SPI mode has no address cycles. The SPI transaction uses latency cycles set by

(CFR3V[7:6]) for reading Volatile registers to enable maximum clock frequency of 166MHz. The HYPERBUS™ trans-

action uses latency cycles set by (CFR1V[7:4]) for reading Volatile registers to enable maximum clock frequency

of 166MHz under HL-T, and 200MHz under HS-T. The HYPERBUS™ mode supports DS for capturing data.

26HS01GTAM03 Datasheet(PDF) 55 Page - Infineon Technologies AG

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