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26HS01GTAM03 Datasheet(PDF) 57 Page - Infineon Technologies AG

Part # 26HS01GTAM03
Description  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 57 Page - Infineon Technologies AG

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Datasheet
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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Features
4.8.4
Data strobe (DS) - HYPERBUS™
To allow for higher data rates, data strobe signal (DS) is added to DDR devices. The data strobe is
non-free-running signal driven by the device, which is also driving the data signals. At the board level, the strobe
signal has identical loading to data signals and needs to be routed similarly. During the period of data transfer in
a read transaction, the Data Strobe (DS) signal is driven by the device and transitions edge aligned with the IO
signal data transitions. DS is used as an additional output signal with the same timing characteristics as other
data outputs but with the guarantee of transitioning with every data bit transferred. The DS signal transitions can
be received and internally phase shifted by the master to be used as an internal read data clock to capture each
data bit transferred.
DS behavior is described as follows:
• DS will start transiting upon valid data
• DS will continue to toggle as long as CS# is low and CK/CK# is toggling. Exceptions to this rule are:
- Inter-page boundary latency
- DS Stall upon detecting an ECC error when reading a Half-page of data.
4.8.5
Burst types
The device supports three burst types during Read transactions:
•Linear Burst
•Wrapped Burst
• Hybrid Burst - HYPERBUS™
Linear burst start at a selected location and output data in a sequential manner (can read the whole memory
array).
Wrapped burst accesses start at a selected location and continue for a configured number of locations in a group
wrap sequence.
Table 47
Example burst sequences
CFR1x
[1:0]
CA[45]
Wrap boundary (bytes)
Start address (hex)
Address sequence (hex) (words)
XX
1
Linear
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, ...
10
0
16
XXXXXX02
02, 03, 04, 05, 06, 07, 00, 01, ...
10
0
16
XXXXXX0C
0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ...
11
0
32
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...
11
0
32
XXXXXX1E
1E, 1F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, ...
01
0
64
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ...
01
0
64
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, ...



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