26HS01GTAM03 datasheet(46/166 Pages) INFINEON

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Datasheet

46 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.5.2.2

Programming SSR memory space

In HYPERBUS™ interface, programming the SSR memory is performed once the SSR ASO is entered using the SSR

Entry sequence. The protocol of the SSR programming command is the same as normal array programming. The

SSR programing sequences can be issued multiple times to any given SSR address, but this address space can

never be erased. The valid address range for SSR Program is depicted in Table 30. SSR Program operations

outside the valid SSR address range will ignore address A9 and higher and will alias into the valid SSR address

range. It is required to align start address to 32 bits while programming SSR space, which means the A0 bit of

address should be 0'b and host should deassert CS# to align with 32 bits. SSR Program operations while

Temporary Locking selection of SSR (CFR1x[10]) = 0 will fail with no indication of the failure. The SSR address

space is not protected by the selection of an ASP Protection mode. A SSR Exit sequence will return the device to

the Read mode.

In Legacy (x1) SPI interface, programming the SSR Region is performed using Read SSR transaction (PRSSR_4_0).

It is required to align start address to 32 bits while programming SSR space, which means the address bits A1 and

A0 should be 0'b and host should deassert CS# to align with 32 bits.

4.5.2.3

HYPERBUS™ SSR related registers and transactions

4.5.2.4

Legacy (x1) SPI SSR related registers and transactions

Table 30

SSR address map

Region

Byte address range (Hex)

Contents

Initial delivery state (Hex)

Region 0

0000h

Least Significant Byte(LSB) of CYPRESS™ Programmed

Random Number

CYPRESS™ Programmed Random Number

...

000Fh

Most Significant Byte (MSB) of CYPRESS™ Programmed

Random Number

0010h–0013h

Region Locking Bits

Byte 10 [bit 0] locks region 0 from programming when = 0

...

Byte 13 [bit 7] locks region 31from programming when = 0

All Bytes = FFh

0014h–001Fh

Reserved for Future Use (RFU)

Region 1

0020h–003Fh

Available for User Programming

Region 2

0040h–005Fh

...

Region 31

03E0h–03FFh

Table 31

HYPERBUS™ SSR related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

N/A

Read Secure Silicon Region (RD_SSR_1_1) - SSR ASO

Program Secure Silicon Region Word (PG_SSR_4_1) - SSR ASO

Load Secure Silicon Region Buffer (LDBSSR_5_1) - SSR ASO

Program Secure Silicon Region Buffer Confirm (PGCSSR_1_1) - SSR ASO

Reset Write to Buffer Abort (RSWSSR_3_1) - SSR ASO

Table 32

Legacy (x1) SPI SSR related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

N/A

Program Secure Silicon Region (PRSSR_4_1)

Read Secure Silicon Region (RDSSR_4_0)

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