26HS01GTAM03 datasheet(63/166 Pages) INFINEON

63 / 166 page

Datasheet

63 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

To calculate latency when crossing a page boundary, use the following formula:

if ((PS - LTCY) < ADDR & (SP -1))

{

((ADDR & (SP -1)) - PS + LTCY)

}

else

{0}

Where:

= Page size = 16 words

= Sub-page size = 8 words

LTCY

= Latency

ADDR

= Target address

Hybrid burst combines one wrapped burst followed by linear burst. The beginning of a hybrid burst will wrap once within the

target address wrapped burst length group, before switching to linear burst of data beyond the end of the initial wrapped burst

length group. Hybrid burst is supported for 16-Byte and 32-Byte but not 64-Byte wrapped burst length groups.

Example burst sequences for 32-Byte, and 16-Byte Hybrid burst reads:

1. 32-Byte example (wrap within 32-Byte boundary before transitioning to linear burst)

a. 06-07-08-09-0A-0B-0C-0D-0E-0F-00-01-02-03-04-05-10-11

b. 0E-0F-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-10-11

2. 16-Byte example (wrap within 16-Byte boundary before transitioning to linear burst)

a. 06-07-00-01-02-03-04-05-08-09

b. 03-04-05-06-07-00-01-02-08-09

4.9

Write transactions - Legacy (x1) SPI

There are write transactions for writing to the Registers.

4.9.1

Write enable transaction

The Write Enable (WRENB_0_0) transaction sets the Write Program Enable Status (WRPGEN) bit of the Status

to enable write, program, and erase transactions.

4.9.2

Write disable transaction

The Write Disable (WRDIS_0_0) transaction clears the Write Program Enable Status (WRPGEN) bit of the Status

The WRPGEN bit can be cleared to 0 by issuing the Write Disable (WRDIS_0_0) transaction to disable commands

that requires WRPGEN be set to 1 for execution. The WRDIS_0_0 transaction can be used by the user to protect

memory areas against inadvertent write, program, or erase operations that can corrupt the contents of the

memory. The WRDIS_0_0 transaction is ignored during an embedded operation while RDYBSY bit = 1 (STR1V[0]).

4.9.3

Clear program and erase failure flags transaction

The Clear Program and Erase Failure Flags (CLPEF_0_0) transaction resets bit STR1V[5] (Erase Error Flag) and bit

STR1V[6] (Program Error Flag) to 0. The Clear Status Register transaction will be accepted even when the device

remains busy with RDYBSY set to 1, as the device does remain busy when either error bit is set. The WRPGEN bit

will be unchanged after this command is executed.

26HS01GTAM03 Datasheet(PDF) 63 Page - Infineon Technologies AG

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