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26HS01GTAM03 Datasheet(PDF) 87 Page - Infineon Technologies AG

Part # 26HS01GTAM03
Description  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 87 Page - Infineon Technologies AG

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Datasheet
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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Features
Figure 46
Exit DPD mode
The device maintains its configuration during DPD, meaning the device exits DPD in the same state as it entered.
Registers such as the ECC Status, ECC Error Detection Counter, Address Trap, and Interrupt Status Registers will
be cleared.
4.16.2.3
HYPERBUS™ DPD related registers and transactions
4.16.2.4
Legacy (x1) SPI DPD related registers and transactions
4.17
Power up and power down
The device must not be selected at power up or power down until VCC reaches the correct value as follows:
•VCC (min) at power up, and then for a further delay of tPU
•VSS at power down
4.17.1
Power up
The device ignores all transactions until a time delay of tPU has elapsed after the moment that VCC rises above
the minimum VCC threshold (see Figure 47). However, correct operation of the device is not guaranteed if VCC
returns below VCC (min) during tPU. No command should be sent to the device until the end of tPU.
The device draws IPOR current during tPU. After power up (tPU), there is the option to be in the DPD mode or
Standby mode. The DPDPOR bit in Configuration Register controls if the device will be in DPD or Standby mode
after the completion of POR. If the DPDPOR bit is enabled, the device is in DPD mode after power up. A Hardware
reset (RESET#) is required to return the device to Standby mode after POR.
Figure 47
Power up
Table 64
HYPERBUS™ DPD related registers and transactions
Related registers
(see Section 5 Registers on page 89)
Related HYPERBUS™ transactions
(see Table 120 on page 124)
Configuration Register 1(CFR1N, CFR1V)
Enter Deep Power Down Mode (ENTDPD_3_0)
Table 65
Legacy (x1) SPI DPD related registers and transactions
Related registers
(see Section 5 Registers on page 89)
Related SPI transactions
(see Table 122 on page 137)
Configuration Register 4 (CFR4N, CFR4V)
Enter Deep Power Down Mode (ENDPD_0_0)



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