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26HS01GTAM03 Datasheet(PDF) 47 Page - Infineon Technologies AG

Part # 26HS01GTAM03
Description  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 47 Page - Infineon Technologies AG

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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Features
4.6
SafeBoot
SEMPER™ Flash memory devices contain an embedded microcontroller which is used to initialize the device,
manage embedded operations, and perform other advanced functionality. An initialization failure of this
embedded microcontroller or corruption of the Nonvolatile Configuration registers can render the flash device
unusable. Barring a catastrophic event, such as permanent corruption of the embedded microcontroller
firmware, it is possible to recover the device.
The SafeBoot feature allows Status Register polling to detect an embedded microcontroller initialization failure
or Configuration Register corruption through error signatures.
4.6.1
Microcontroller initialization failure detection (x1 boot option)
If the microcontroller embedded in the flash device fails to initialize, a hardware reset can recover the device,
unless it is a catastrophic failure. This hardware reset must be initiated by the Host controller. Upon detecting a
failed microcontroller initialization, the flash device automatically reverts to Legacy (x1) SPI Interface and
provides a failure signature in its Status Register.
Table 33 shows the device’s Status Register bits upon detecting an initialization failure.
Table 33
Status register 1 power-on detection signature
Bit
Field name
Function
Detection signature
STR1V[7]
RESVRD
Reserved for Future Use
0
STR1V[6]
PRGERR
Programming Error Status Flag
1
STR1V[5]
ERSERR
Erasing Error Status Flag
1
STR1V[4]
RESVRD
Reserved for Future Use
0
STR1V[3]
0
STR1V[2]
0
STR1V[1]
WRPGEN
Write/Program Enable Status Flag
0
STR1V[0]
RDYBSY
Device Ready/Busy Status Flag
1
Table 34
Interface configuration upon detecting power-on failure[18]
Interface
Transactions supported
Register type
Address
(# of Bytes)
Frequency of
operation
Register read
latency (# of clock
cycles)
Output
impedance
SPI
(1S-1S-1S)
Read Status Register 1
(RDSR1_0_0)
Read Any Register
(RDARG_4_0)
Status Register (Volatile
Only)
4
Maximum
(allowed for
RDSR1_0_0,
RDARG_4_0)
2
45 
Note
18. For reading the Status Register, providing the Nonvolatile Status Register address to RDARG_4_0 will produce indeterminate results.



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