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26HS01GTAM03 Datasheet(PDF) 1 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 1 Page - Infineon Technologies AG |
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1 / 166 page  Datasheet Please read the Important Notice and Warnings at the end of this document 002-12337 Rev. *Y www.infineon.com page 1 of 166 2022-01-18 S26HS256T, S26HS512T, S26HS01GT, S26HL256T, S26HL512T, S26HL01GT 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Features • CYPRESS™ 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell • Sector architecture options - Uniform: Address space consists of all 256KB Sectors -Hybrid • Configuration 1: Address space consists of thirty-two 4KB sectors grouped either on the top or the bottom while the remaining sectors are all 256KB • Configuration 2: Address space consists of thirty-two 4KB sectors equally split between top and bottom while the remaining sectors are all 256KB • Page Programming buffer of 256 or 512 bytes • OTP secure silicon region (SSR) of 1024 bytes (32 32 bytes) • HYPERBUS™ interface - JEDEC eXpanded SPI (JESD251) compliant - DDR option runs up to 400-MBps (200MHz clock speed) - Supports data strobe (DS) to simplify the read data capture in high-speed systems • Legacy (x1) SPI (1S-1S-1S) - JEDEC eXpanded SPI (JESD251) compliant - SDR option runs up to 21-MBps (166MHz clock speed) • SEMPER™ Flash with HYPERBUS™ interface devices support default boot in legacy SPI (x1) or HYPERBUS™ interface (x8) • Functional safety features - Functional safety ISO26262 ASIL B compliant and ASIL D ready -Infineon endurance flex architecture provides high-endurance and long retention partitions - Interface CRC detects errors on communication interface between host controller and SEMPER™ Flash device - Data integrity CRC detects errors in memory array - SafeBoot reports device initialization failures, detects configuration corruption, and provides recovery options - Built-in error correcting code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory array data - Sector erase status indicator for power loss during erase •Protection features - Advanced sector protection for individual memory array sector based protection • AutoBoot enables immediate access to the memory array following power-on • Hardware reset through CS# signaling method (JEDEC) AND individual RESET# pin • Serial flash discoverable parameters (SFDP) describing device functions and features • Device identification, manufacturer identification and unique identification • Data integrity - 256Mb devices • Minimum 640,000 program-erase cycles for the main array - 512Mb devices • Minimum 1,280,000 program-erase cycles for the main array |
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