26HS01GTAM03 datasheet(29/166 Pages) INFINEON

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Datasheet

29 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.1.1.3

ECC error detection counter (ECTV)

• A 16-bit register is provided to count the number of 1-bit or 2-bit errors that occur as data is read from the flash

memory array. Only errors recognized in the main array will cause the Error Detection Counter to increment.

ECTV Register is only updated during Read transaction. Read ECC Status transaction does not affect the ECTV

The 16-bit Error Detection Counter will not increment beyond FFFFh. However, the ECC continues to work.

Note that during continuous read operations, when a 1-bit or a 2-bit error is detected, the clock may continue

toggling and the memory device will continue incrementing the data address and placing new data on the DQ

signals; any additional data units with errors that are encountered will be counted until CS# is brought back

HIGH.

During a read transaction only one error is counted for each data unit found with an error. Each read transac-

tion will cause a new read of the target data unit. If multiple read transactions access the same data unit

containing an error, the error counter will increment each time that data unit is read.

When 2-bit error detection is not enabled and the same data unit is programmed more than once, ECC error

detection for that data unit is disabled so, no error can be recognized or counted.

• The ECC Error Detection Counter Register can be read using HYPERBUS™ or Legacy (x1) SPI ECC Error Detection

Counter read transaction.

• ECTV Register is set to 0 on POR, CS# Signaling/Hardware/Software Reset or with Clear ECC Status Register

transaction.

Table 12

Error detection counter (Volatile)

Bit position

EDC result

EDC[15]

R15

EDC[14]

R14

EDC[13]

R13

EDC[12]

R12

EDC[11]

R11

EDC[10]

R10

EDC[9]

EDC[8]

EDC[7]

EDC[6]

EDC[5]

EDC[4]

EDC[3]

EDC[2]

EDC[1]

EDC[0]

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