26HS01GTAM03 datasheet(73/166 Pages) INFINEON

73 / 166 page

Datasheet

73 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

Figure 37

Sector erase operation

4.11.2.1

Erase register transactions

The Erase Register (ERNC12_3_0) transactions provide a way to erase any Nonvolatile Device Register. The trans-

actions include unlock cycles.

The ERSERR bit in STRV[5] may be checked to determine if any error occurred during the operation.

4.11.2.2

Erase persistent protection bits (PPB)

The Erase Persistent Protect Bits (ERNPPB_2_1) transaction erases all PPB bits.

The ERSERR bit in STRV[5] may be checked to determine if any error occurred during the operation. Erase PPB

bit transaction will abort when trying to erase the PPB bits protected by PPBLCK (PPLV[0]) bit.

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Address 2AAh, Data 55h

Sector Address, Data 30h

FAIL. Write reset command

to return to reading array.

PASS. Device returns

to reading array.

Perform Write Operation

Status Algorithm

Unlock Cycle 1

Unlock Cycle 2

Yes

Done?

Erase Error?

Command Cycle 1

Command Cycle 2

Command Cycle 3

Specify first sector for erasure

Error condition (Exceeded Timing Limits)

Status may be obtained by Status Register Polling.

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