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26HS01GTAM03 Datasheet(PDF) 56 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 56 Page - Infineon Technologies AG |
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56 / 166 page  Datasheet 56 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Features 4.8.3.7 Read ECC data unit status The Read ECC Data Unit Status (RDECC_4_0, RDECST_1_1) transaction is used to determine the ECC status of the addressed unit data. In this transaction, the LSb of the address must be aligned to an ECC data unit. The SPI transaction uses latency cycles set by (CFR3V[7:6]) for reading Volatile registers to enable maximum clock frequency of 166MHz. The HYPERBUS™ transaction uses latency cycles set by (CFR1V[7:4]) for reading Volatile registers to enable maximum clock frequency of 166MHz under HL-T, and 200MHz under HS-T. The HYPERBUS™ mode supports DS for capturing data. In SPI mode, the device outputs the byte contents of the ECC Status for the selected ECC unit. In HYPERBUS™ mode, the device outputs the word contents of the ECC status for the selected ECC unit. To read the next ECC unit status, another Read ECC Data Unit Status transaction must be initiated to the next ECC data unit aligned address - incremented by 16 bytes. 4.8.3.8 Read POR timer transaction - HYPERBUS™ The Read Power-On-Reset Timer (RDNPOR_4_0) transaction is used to read the contents of the POR Timer Register. This transaction uses latency cycles set by (CFR1V[7:4]) to enable maximum clock frequency of 166MHz under HL-T, and 200MHz. under HS-T. The HYPERBUS™ mode supports DS for capturing data. The POR Timer Register controls the functionality of the RSTO# pin. 4.8.3.9 HYPERBUS™ read register related registers and transactions 4.8.3.10 Legacy (x1) SPI read register related registers and transactions Table 45 HYPERBUS™ read register related registers and transactions Related registers (see Section 5.2 HYPERBUS™ registers on page 90) Related HYPERBUS™ transactions (see Table 120 on page 124) HYPERBUS™ Configuration Register 1 (CFR1N, CFR1V) Read ID/Unique ID/SFDP (RDIDSF_1_1) - Device ID/ Unique ID/SFDP ASO Read Status Register (RDVSTR_2_0) Read Volatile Configuration Register 1 (RDVCR1_4_0) Read Volatile Configuration Register 2 (RDVCR2_4_0) Read Nonvolatile Configuration Register 1 (RDNCR1_4_0) Read Nonvolatile Configuration Register 2 (RDNCR2_4_0) Read Nonvolatile Persistent Protection Bits (RDNPPB_1_1) Read Volatile Persistent Protection Lock (RDVPPL_1_1) Read Volatile Dynamic Protection Bits (RDVDYB_1_1) Read Error Correction (ECC) Status (RDECST_1_1) Read Nonvolatile POR Timer Register (RDNPOR_4_0) Table 46 Legacy (x1) SPI read register related registers and transactions Related registers (see Section 5.3 Legacy (x1) SPI registers on page 106) Related SPI transactions (see Table 125 on page 141) SPI Configuration Register 2 (CFR2N, CFR2V) Read Device ID (RDIDN_0_0) SPI Configuration Register 3 (CFR3N, CFR3V) Read SFDP (RSFDP_3_0) |
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