26HS01GTAM03 datasheet(31/166 Pages) INFINEON

31 / 166 page

Datasheet

31 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.2

Infineon® Endurance Flex architecture (wear leveling)

Infineon Endurance Flex architecture allows partitioning of the main memory array into regions which can be

configured as either high endurance or long retention. Endurance Flex implements wear leveling in high

endurance regions where program/erase cycles are spread evenly across all the sectors which are part of the wear

leveling pool. This greatly improves the reliability of the device by avoiding premature wear-out of an individual

sector.

Architecturally, Endurance Flex’s wear leveling algorithm is based on a mapping of logical sectors to physical

sectors. During the lifetime of the part, this mapping is changed to maintain a uniform distribution of

program/erase cycles over all physical sectors. The logical to physical mapping information is stored in a

dedicated flash array which is updated when sectors are swapped. Sector swaps occur when an erase transaction

is given.

Endurance Flex’s high endurance region requires a minimum set of 20 sectors. To provide flexibility between

configuring long retention, high endurance, or both regions, a four pointer architecture is provided. The factory

default setting designates all sectors as high endurance as part of the wear leveling pool with all pointers

disabled. The four pointers can be used to form a maximum of five regions which can each be configured as long

retention or high endurance.

Figure 20 provides an overview of the Infineon Endurance Flex architecture. It shows the five possible regions

based on different sector architecture.

Note 4KB sectors are not part of the Infineon Endurance Flex architecture.

Figure 20

Infineon Endurance Flex architecture overview

26HS01GTAM03 Datasheet(PDF) 31 Page - Infineon Technologies AG