26HS01GTAM03 datasheet(104/166 Pages) INFINEON

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Datasheet

104 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.2.18

INT# pin configuration register (INCV) (x8)

The INT# pin Configuration Register (INCV) configures which internal event will trigger a High to Low transition

on the INT# output pin.

Table 88

Infineon Endurance Flex architecture selection register (Pointer 0) (x8)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

EFX0[1]

GBLSEL

All Sectors based

Region type Selection

N => R/1

Description: The GBLSEL bit defines whether all sectors

are defined as long retention region or high endurance

region.

Note If all other Pointer registers are disabled, this bit

defines the behavior of the entire memory space and is

hardwired to start at Sector 0.

Selection Options:

0 = Long Retention Sectors

1 = High Endurance Sectors

Dependency: N/A

EFX0[0]

WRLVEN

Wear Leveling Enable

Selection

N => R/1

Description: The WRLVEN bit enables/disables the wear

leveling feature.

Selection Options:

0 = Wear Leveling Disabled

1 = Wear Leveling Enabled

Dependency: N/A

Table 89

Interrupt configuration register (x8)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

INCV[15]

INTBEN

INT# pin Enable

Selection

V => R/W

Description: The INT# pin is an open-drain output used

to indicate to the host system that an event has

occurred within the memory device. The INTBEN bit

enables or disables the functionality controlling INT#

pin.

Selection Options:

0 = INT# pin functionality is enabled

1 = INT# pin functionality is disabled

Dependency: N/A

INCV[14]

RESRVD

Reserved for Future Use

V => R/W

These bits are Reserved for future use. This bit must

always be written/loaded to its default state.

INCV[13:5]

RESRVD

Reserved for Future Use

V => R/W

111111111 These bits are Reserved for future use. This bit must

always be written/loaded to its default state.

INCV[4]

REYBSY

Ready/Busy Transition

Selection

V => R/W

Description: The REYBSY bit enables or disables

whether device ready/busy state will transition INT#.

Selection Options:

0 = A Busy to Ready transition will cause a High to Low

transition on the INT# output

1 = Ready/Busy transitions will not transition the INT#

output

Dependency: N/A

INCV[3:2]

RESRVD

Reserved for Future Use

V => R/W

These bits are Reserved for future use. This bit must

always be written/loaded to its default state.

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