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26HS01GTAM03 Datasheet(PDF) 107 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 107 Page - Infineon Technologies AG |
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107 / 166 page ![]() Datasheet 107 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Registers STR1V[1] WRPGEN Write/Program Enable Status Flag V -> R 0 Description: The WRPGEN bit must be set to ‘1’ to enable all program, erase or register write operations - it provides protection against inadvertent changes to memory or register values. The Write Enable (WRENB_0_0) and Write Enable Volatile (WRENV_0_0) transactions set the WRPGEN bit to ‘1’ to allow program, erase or write transactions to execute. The Write Disable (WRDIS_0_0) transaction resets WRPGEN to a ‘0’ to prevent all program, erase, and write transactions from execution. The WRPGEN bit is cleared to ‘0’ at the end of any successful program, erase or register write operation. After a power down / power up sequence or a hardware/software reset, the Deep Power Down WRPGEN bit is cleared to ‘0’. Selection Options: 0 = Program, erase or register write is disabled 1 = Program, erase or register write is enabled Dependency: N/A STR1V[0] RDYBSY Device Ready/Busy Status Flag V -> R 0 Description: The RDYBSY bit indicates whether the device is performing an embedded operation or is in standby mode ready to receive new transactions. Note The PRGERR and ERSERR status bits are updated while RDYBSY is set. If PRGERR or ERSERR are set, the RDYBSY bit will remain set indicating the device is busy and unable to receive new transactions. A Clear Status Register (CLSTR_0_0) transaction must be executed to return the device to standby mode. Selection Options: 0 = Device is in standby mode ready to receive new operation transactions 1 = Device is busy and unable to receive new operation transactions Dependency: N/A Table 91 Status register 1 (x8)[25] (Continued) Bit number Name Function Read/write N = Nonvolatile V = Volatile Factory default (binary) Description Note 25. STR1x value during POR, Hardware Reset, DPD Exit, and CS# Signaling Reset is not valid. |
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