26HS01GTAM03 datasheet(110/166 Pages) INFINEON

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Datasheet

110 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.3.4

Configuration register 2 (CFR2x) (x1)

Configuration Register 2 controls the memory read latency selection.

Table 94

4KB parameter sector location selection

SP4KBS

TB4KBS

4KB location

4KB physical sectors at bottom (Low address)

4KB physical sectors at top, (High address)

4KB Parameter sectors are split between top (High Address) and bottom (Low Address)

Table 95

PLPROT and TLPROT protection

PLPROT

TLPROT

Array protection and 4K sector

Unprotected (Unlocked)

TBPROT, SP4KBS, TB4KBS - Permanently Protected (Locked)

TBPROT, SP4KBS, TB4KBS - Protected (Locked) till next Power-down

Table 96

Configuration register 2 (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

CFR2N[7]

CFR2V[7]

ADRBYT

Address Byte Length

selectionbetween3or4

bytes for Instructions

N -> R/W

V -> R/W

Description:

The ADRBYT bit controls the expected address length for all

instructions that require address and is selectable between

3 Bytes or 4 Bytes.

Selection Options:

0 = Instructions will use 3 Bytes for address

1 = Instructions will use 4 Bytes for address

Dependency: N/A

CFR2N[6:4]

CFR2V[6:4]

RESRVD

Reserved for Future Use

N -> R/W

V -> R/W

000

These bits are Reserved for future use. This bit must always

be written/loaded to its default state.

CFR2N[3:0]

CFR2V[3:0]

MEMLAT[3:0]

Memory Array Read

Latency selection -

Dummy cycles required

for initial data access

N -> R/W

V -> R/W

1000

Description: The MEMLAT[3:0] bits control the read latency

(dummy cycles) delay in all variable latency memory array

and Nonvolatile Register read transactions. MEMLAT

selection allows the user to adjust the read latency during

normal operation based on different operating frequencies.

Selection Options:

0000 = 0 Latency Cycles Selection based on transaction

opcodes

…..

1111 = 15 Latency Cycles Selection based on transaction

opcodes

Dependency: N/A

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