26HS01GTAM03 datasheet(114/166 Pages) INFINEON

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Datasheet

114 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.3.6

Configuration register 4 (CFR4x) (x1)

Configuration Register 4 controls the main flash array read transactions burst wrap behavior and output driver

impedance.

Table 100

Configuration register 4 (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

CFR4N[7:5]

CFR4V[7:5]

IOIMPD[2:0]

I/O Driver Output

Impedance selection

N -> R/W

V -> R/W

101

Description: The IOIMPD[2:0] bits select the IO driver

output impedance (drive strength). The output

impedance configuration bits adjust the drive strength

during normal device operation to meet system signal

integrity requirements.

Selection Options:

000 = 45Ω

001 = 120Ω

010 = 90Ω

011 = 60Ω

100 = 45Ω

101 = 30Ω (Factory Default)

110 = 20Ω

111 = 15Ω

Dependency: N/A

CFR4N[4]

CFR4V[4]

RBSTWP

Read Burst Wrap Enable

selection

N -> R/W

V -> R/W

Description: The RBSTWP bit selects the read burst wrap

feature. It allows the device to enter and exit burst

wrapped read mode during normal operation. The wrap

length is selected by RBSTWL[1:0] bits.

Selection Options:

0 = Read Wrapped Burst disabled

1 = Read Wrapped Burst enabled

Dependency: RBSTWL[1:0] (CFR4x[1:0])

CFR4N[3]

CFR4V[3]

ECC12S

Error Correction Code

(ECC) 1-bit or 1-bit/2-bit

error correction

selection

N -> R/W

V -> R/W

Description: The ECC12S bit selects between 1-bit ECC

error detection/correction or both 1-bit ECC error

detection and correction and 2-bit ECC error detection.

This configuration option affects Address Trap Register

and ECC Counter Register functionalities as well. The

host needs to erase and reprogram the data in the

SEMPER™ Flash memory upon ECC configuration

change (1-bit correction to 1-bit correction and 2-bit

detection or vice versa).

Selection Options:

0 = 1-bit ECC Error Detection/Correction

1 = 1-bit ECC Error Detection/Correction and 2-bit ECC

error detection

Dependency: N/A

CFR4N[2]

CFR4V[2]

DPDPOR

Deep Power Down

power saving mode

entry selection upon

POR

N -> R/W

V -> R

Description: The DPDPOR bit selects if the device will be

in either Deep Power Down (DPD) mode or the Standby

mode after the completion of POR. If enabled, DPDPOR

configures the device to start in DPD mode to reduce

current consumption until the device is needed. If the

device is in DPD, a pulse on CS# or a Hardware reset will

return the device to Standby mode.

Selection Options:

0 = Standby mode is entered upon the completion of

POR

1 = Deep Power Down Power mode is entered upon the

completion of POR

Dependency: N/A

CFR4N[1:0]

CFR4V[1:0]

RBSTWL[1:0]

ReadBurst WrapLength

selection

N -> R/W

V -> R/W

Description: The RBSTWL[1:0] bits select the read burst

wrap length and alignment during normal operation. It

selects the fixed length/aligned group of 8-, 16-, 32-, or

64-bytes.

Selection Options:

00 = 8 Bytes Wrap length

01 = 16 Bytes Wrap length

10 = 32 Bytes Wrap length

11 = 64 Bytes Wrap length

Dependency: RBSTWP (CFR4x[4])

26HS01GTAM03 Datasheet(PDF) 114 Page - Infineon Technologies AG

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