26HS01GTAM03 datasheet(113/166 Pages) INFINEON

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Datasheet

113 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

CFR3N[1]

CFR3V[1]

INTFTP

Interface type selection

between HYPERBUS™

and Legacy (x1) SPI

N -> R/W

V -> R/W

The INTFTP bit selects the interface of the device

between HYPERBUS™ and legacy (x1) SPI.

Selection Options:

1 = HYPERBUS™ interface

0 = Legacy (x1) SPI

Dependency: N/A

CFR3N[0]

CFR3V[0]

RESRVD

Reserved for Future Use

N -> R/W

V -> R/W

This bit is Reserved for future use. This bit must always

be written/loaded to its default state.

Table 99

Latency code

SDR SPI register transaction latency dummy cycles (1S-1S-1S)[32, 34]

Frequency[31]

RDARG_4_0[33]

RDDYB_4_0

RDPLB_0_0

RDIDN_0_0

RDSR1_0_0

RDSR2_0_0

50MHz

133MHz

166MHz

Table 98

Configuration register 3 (x1) (Continued)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

Notes

31. SCK frequency > 166MHz SDR, is not supported.

32. RDUID_4_0 alway has 32 cycles of latency. Maximum frequency under SDR SPI is 166MHz, under HS-T SDR/DDR Octal is 200MHz and under HL-T

SDR/DDR Octal is 166MHz.

33. RDARG_4_0 uses these dummy cycles for reading Volatile registers.

34. RDCRC_4_0 alway has 8 cycles of latency. Maximum frequency under SDR SPI is 166MHz, under HS-T SDR/DDR Octal is 200MHz and under HL-T SDR/DDR

Octal is 166MHz.

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