26HS01GTAM03 datasheet(115/166 Pages) INFINEON

115 / 166 page

Datasheet

115 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.3.7

Interface CRC enable register (ICEV) (x1)

Interface CRC Enable Register controls the enabling/disabling of the Interface CRC function.

5.3.8

Interface CRC check-value register (ICRV) (x1)

The Interface CRC Check-value Register (ICRV) stores the results of the CRC calculation on the command and Data

Content over the interface for Protection.

Table 101

Output data wrap sequence

Wrap boundary (Bytes)

Start address (Hex)

Address sequence (Hex)

Sequential

XXXXXX03

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18.

XXXXXX00

00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02.

XXXXXX07

07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01.

XXXXXX02

02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03.

XXXXXX0C

0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E.

XXXXXX0A

0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E,

1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F.

XXXXXX1E

1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12,

13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00.

XXXXXX03

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17,

18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C,

2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F 00, 01, 02.

XXXXXX2E

2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02,

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17,

18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D.

Table 102

Interface CRC enable register (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

ICEV[7:1]

RESVRD

Reserved for Future Use

V -> R

0000000

This bit is Reserved for future use. This bit

must always be written/loaded to its default

state.

ICEV[0]

ITCRCE

Interface CRC Selection

V -> R/W

Description: The ITCRCE bit controls

enabling/disabling of the Interface CRC

function.

Selection Options:

0 = Interface CRC Enabled

1 = Interface CRC Disabled

Dependency: N/A

Table 103

Interface CRC check-value register (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(hex)

Description

ICRV[31:0]

ITCRCV[31:0]

Interface CRC

Checksum Value

V -> R

0xFFFFFFFF

Description: The ITCRCV[31:0] bits store the

check-value of the CRC process on the

memory array data contained within the

starting address and the ending address.

Selection Options: Checksum Value

Dependency: N/A

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